The invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a non-volatile memory device.
When a non-volatile memory device, e.g., a flash memory device, has a minimum line width of less than approximately 100 nm, interference phenomena between mutually adjacent unit cells become more problematic. During data program, erase, and read operations, interference phenomena of flash memory devices frequently. Interference phenomena between floating gates (FGs) and between a control gate (CG) and a channel on a substrate make up a large percentage of various interference phenomena of such semiconductor devices. Due to these interference phenomena, there are limitations to improvements in the degree of integration for an ultrafine flash memory device.
To overcome these limitations, a method of fabricating a trench device isolation layer has attracted much interest; this method takes advantage of a self aligned-shallow trench isolation (SA-STI) technique. Moreover, to enhance filling characteristics, a method of using a spin on dielectric (SOD) layer as a trench filling insulation layer is being noted with great interest. According to the SA-STI technique, after forming a tunnel oxide layer on a substrate in order to expose a device isolation region of the substrate and also a pattern of a floating gate electrode layer, the exposed portion of the substrate is etched in order to allow a trench for device isolation to be aligned on the floating gate electrode pattern. Next, the trench is filled with the filling insulation layer to form a trench device isolation layer.
Although an SA-STI structure may be useful in increasing the degree of integration of a device, interference phenomena still occur. For example, when forming a device isolation layer through the SA-STI technique, the following limitations may arise. If the effective field height (EFH) of a formed device isolation layer is too high, interference phenomena occur between adjacent floating gate electrodes. If the EFH of the device isolation layer is too low, interference phenomena also arise because an interval between a control gate electrode and a channel region in a semiconductor substrate becomes closer. On the other hand, when the SOD layer is used as a trench filling insulation layer, it is advantageous for filling the narrowed inside of a trench. However, the surface of a SOD insulating layer may be exposed during subsequent processes. In this case, due to vulnerable wet etching characteristics of the SOD layer, loss of the exposed SOD layer during the subsequent processes may occur. Consequently, reliability of a device can be deteriorated.